The present disclosure relates generally to semiconductor manufacturing and, more particularly, to a method for etching an ultra thin film in semiconductor manufacturing.
An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a semiconductor substrate using a fabrication process. As fabrication processes and materials improve, semiconductor device geometries have continued to decrease in size since such devices were first introduced several decades ago. For example, current fabrication processes are producing semiconductor devices with 45 nm process technology and beyond. However, the reduction in size of device geometries frequently introduces new challenges that need to be overcome.
As semiconductor devices are scaled down, various ultra thin films having a thickness of less than 100 Angstroms have been employed. For example, ultra thin SiO2 gate oxide dielectric films may be used in semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs) and complementary metal-oxide-semiconductor (CMOS) devices. However, current techniques for patterning ultra thin films have not been satisfactory in all respects. In particular, it has been increasingly difficult to control the etching of ultra thin films without causing lateral etching of the ultra thin film underneath a photoresist layer. Accordingly, patterns formed in the ultra thin film may vary and be distorted which can lead to various problems such as poor device performance and low yield.
Therefore, a need exists for a simple and cost-effective method for etching an ultra thin film in semiconductor devices.